Dual Independent Bus Architecture

Technical Background

The Pentium® II processor combines Intel’s three latest technology advancements into a new generation of products to achieve the next level of performance required by today’s software applications. These features are MMX™ technology, Dynamic Execution and the Dual Independent Bus Architecture. The Dual Independent Bus Architecture unleashes the power of the Dynamic Execution engine by providing up to three times the bandwidth available to the processor core, than is available with the Pentium processor bus architecture.

Dynamic Execution
The Dynamic Execution architecture is a unique combination of multiple branch prediction, speculative execution, and data flow analysis. These features allow the Pentium II processor to dispatch up to 5mops per clock to its execution unit. (mops are low level machine instructions which combine in many ways to make up the rich instruction set of the Intel Architecture.)

Because some instructions are dependent on data residing in cache or the main memory system, or simply take many clocks to execute, the Pentium II processor speculatively fetches and executes instructions that follow the long latency instruction in order to most efficiently use the processor core and the external busses. In speculatively executing instructions, branches may be taken, and good branch prediction becomes very important. The Pentium II processor is capable of taking multiple predicted branches rather than stalling upon the first or second branch instruction that occurs. The data flow analysis makes all of this possible while ensuring that all data dependencies are resolved prior to instruction retirement and that the external busses available to the processor core are efficiently utilized.

The increase in activity per clock produced by the dynamic execution architecture is precisely what allows the Pentium II processor to perform significantly faster that the Pentium processor. As would be expected, more instructions per clock causes more bus activity per clock.

Bandwidth
Bandwidth can used to easily compare the capabilities of various bus architectures. The peak bandwidth of a bus can be calculated by multiplying the operation frequency of the bus by the number of bytes transferred per clock, or the width of that bus. The Pentium processor operates at a system bus frequency of 66.67MHz and is an 8-byte wide bus. Therefore the peak bandwidth of the Pentium processor bus is 66.67 x 8 or about 533MB/sec.

When a processor core is running at a frequency greater than the system bus frequency, and/or is capable of executing multiple instructions per clock, it becomes possible to completely consume the available bandwidth of the system bus. This results in a bottleneck that can severely limit the processor execution engine. Increasing bandwidth requires either increasing the frequency or the width of the bus.

Previous Generation Bus

Small increases in the frequency of the system bus have been achievable, but technology advances have not been able to keep up with the demands of the processor core. To illustrate, a processor core running at 200MHz is a 300% speedup over a 66.67MHz processor. Today’s technology allows for a system bus to run at perhaps 75MHz, but only provides a 12.5% speedup over the 66.67MHz bus.

To overcome this issue, Intel has created the Dual Independent Bus Architecture.

Dual Independent Bus Architecture
Two buses make up the Dual Independent Bus architecture: the L2 cache bus and the system bus. Each is 8-bytes wide, thus doubling the available channels for data. As the L2 cache bus is integrated into the Single Edge Contact cartridge, it is not limited in speed by the constraints of motherboard routing. Therefore the L2 cache bus is designed to run at 1/2 the processor core frequency on the Pentium II processor.

Dual Independent Bus Architecture
[Dual Independent Bus Architecture diagram]

Peak bandwidth for a Pentium II processor with Dual Independent Bus Architecture can be calculated as 533MB/sec for the system bus plus 8 times the L2 cache bus frequency. This provides for peak bandwidths as shown in the following table:

Processor	Total Peak Bandwidth
Standard Pentium processor	533 MB/sec
Pentium processor with 75MHz bus	600 MB/sec
233 MHz Pentium II processor	1466 MB/sec
266 MHz Pentium II processor	1600 MB/sec
300 MHz Pentium II processor	1733 MB/sec

As can be readily seen, the 266MHz Pentium II processor has 3 times the bandwidth of a 66MHz Pentium processor due to the Dual Independent Bus Architecture. In addition, bus bandwidth increases with processor core frequency providing a path for future generations of processors.

¹ Intel chose not to develop a 75MHz system bus as this provides only a 12.5% increase over a 66.67MHz bus.